The present invention relates to a PLL circuit that generates a clock signal used to control the recording of data to, for example, a disc medium, and a data recording controller.
Disc media, such as an optical disc, is nowadays widely used as recording media. Data recordable recording media include, for example, a digital versatile disc-recordable (DVD-R) and a digital versatile disc-rewritable (DVD-RW). A DVD-RW includes a track, which is formed by grooves between lands. The grooves are slightly wobbled. This enables a wobble signal having a predetermined cycle to be extracted from the wobbled grooves. The wobbling is formed in correspondence with a data recording region, which is in a DVD data format and has a predetermined data length.
In addition to the wobbling, the disc medium has land prepits (LPPs), which include disc position information, formed at predetermined intervals along the track. An LPP signal is generated by reproducing the LPPs. The LPP signal is generated at a rate of 1 to 3 pulses per 16 pulses of the wobble signal. Disc position information is retrieved from the LPP signal.
A laser beam is emitted on to the disc medium, the rotation of which is controlled, to record data on the disc medium. When recording data, it is preferred that the data recording be performed in accordance with a reference clock signal corresponding to the rotation of the disc medium. By using the reference clock signal, the recording region for one bit of data recorded on the disc medium is constant. Thus, the recoding of data is accurately controlled.
The reference clock signal is acquired by reproducing the wobble signal and generating a pulse signal, which is synchronized with the wobble signal, with a PLL circuit. More specifically, a phase comparator compares the phases of the clock signal, the oscillation of which is controlled by a voltage-controlled oscillator, and the wobble signal. The voltage corresponding to the frequency difference or phase difference of the two signals is fed back to the voltage-controlled oscillator to synchronize the clock signal, which is generated by the voltage-controlled oscillator, with the wobble signal.
When generating the reference clock signal with the PLL circuit, it is preferred that the LPP signal be used instead of the wobble signal. However, the frequency of the LPP signal is lower than that of the wobble signal. In addition, since there are only one to three LPP signal pulses for every pulse of the wobble signal, the LPP signal pulses do not necessarily correspond with the 16 pulses of the wobble signal. Thus, it is difficult to generate a clock signal that is accurately synchronized with the LPP signal;
In addition to the LPP signal and the wobble signal, under circumstances in which there are two signals having different frequencies, the same problem occurs when generating a clock signal synchronized with a signal, which is not easily synchronized with since its pulses do not appear frequently.